1. Technical Field
The present invention relates to a wafer level package, a chip size package device, and a wafer level package manufacturing method, in which plural chips are mounted on or formed in a plane of a first wafer and a second wafer is joined to the first wafer to seal each chip using a seal frame. Particularly, the present invention relates to a wafer level package that can avoid generation of a crack in the seal frame during dicing and reduce generation of separation in the wafer even if the wafer is subjected to a high-temperature process after a wet process or liquid cleaning.
2. Related Art
Nowadays, downsizing, weight reduction, and high functionality make dramatic progress in electronic products typified by a mobile phone, a mobile computer, a personal digital assistance (PDA), and a digital still camera (DSC) and the like. With a market trend of the electronic products, there is also a strong demand for the downsizing, a low profile, the weight reduction, and high-density packaging into a mounting board for a semiconductor package mounted on the electronic product.
A new semiconductor package technology called a wafer level package in which processes are performed up to packaging in a wafer state receives attention against this background. In the wafer level package, re-wiring, electrode formation, resin sealing, and dicing are thoroughly performed in the wafer process, a size of the semiconductor chip into which the wafer is finally cut directly becomes a size of the package. Therefore, the wafer level package is ideal technology from the viewpoints of the downsizing and the weight reduction, and is already used in the mobile phone and the like.
Specifically, Patent Documents 1 to 3 disclose conventional technologies for the wafer level package.
In a wafer level package 100 disclosed in Patent Document 1, as illustrated in FIG. 9, a cover wafer 102 including an external electric terminal 101 is disposed on a substrate wafer 104 on which plural semiconductor chips 103 are mounted, each semiconductor chip 103 is sealed with a seal ring 105 that is of a seal frame by joining the cover wafer 102 to the substrate wafer 104, and an electric contact between the external electric terminal 101 of the cover wafer 102 and the semiconductor chips 103 mounted on the substrate wafer 104 is established by a conductive route 106.
In the wafer level package 100, all peripheries of the semiconductor chips 103, . . . are formed by the seal ring 105 as illustrated in FIGS. 10(a) and 10(b), and the seal ring 105 is diced on dicing lines 107 to segmentalize the wafer level package 100 into individual packages as illustrated in FIGS. 11(a) and 11(b).
In a wafer level package 200 disclosed in Patent Document 2, a cap wafer 201 made of silicon (Si) and a base wafer 203 which a device 202 is mounted on or formed in are joined as illustrated in FIGS. 12(a) and 12(b). In the joined portion, a gasket 204 that is of the seal ring formed by partially removing the cap wafer 201 and the base wafer 203 are bonded by a joining material 205, and a spatial portion in the gasket 204 is sealed by a resin 206.
In the wafer level package 200, a gap 207 exists between the gaskets 204 and 204 in the peripheries of the devices 202 adjacent to each other as illustrated in FIGS. 13(a) and 13(b), and the wafer level package 200 is diced in the gap 207 and segmentalized into the individual packages as illustrated in FIGS. 14(a) and 14(b).
The wafer level package disclosed in Patent Document 3 has the configuration similar to that of the wafer level package 200 disclosed in Patent Document 2.    Patent Document 1: Japanese Unexamined Patent Publication No. 6-318625 (Published on Nov. 15, 1994)    Patent Document 2: Japanese Unexamined Patent Publication No. 2003-204005 (Published on Jul. 18, 2003)    Patent Document 3: U.S. Patent Application No. 2009/0194861 (Published on Aug. 6, 2009)